Liquid crystal displays are used in various fields ranging from small portable telephones to large television sets exceeding 30 inches in size. They are classified into those of simple matrix type and those of active matrix type. The latter have thin film transistors (TFT for short hereinafter) as the switching elements and find general use because of their high definition image quality and their ability to reproduce high-speed animations.
The following is a description of the structure and working principle of a typical liquid crystal display used for liquid crystal displays of active matrix type, which is given with reference to FIG. 1. The liquid crystal display has a TFT substrate with an active semiconductor layer of hydrogenated amorphous silicon. (The TFT substrate may occasionally be referred to as an amorphous silicon TFT substrate hereinafter.)
As shown in FIG. 1, the liquid crystal display panel 100 consists of a TFT substrate 1, an opposite substrate 2 facing the TFT substrate 1, and a liquid crystal layer 3 (as a light modulating layer) held between the two substrates. The TFT substrate 1 is an insulating glass plate 1a supporting thereon TFTs 4, transparent pixel electrodes 5, and wiring 6 such as scanning lines and signal lines. The transparent pixel electrodes 5 are formed from ITO film. (ITO is a mixture of indium oxide In2O3 and about 10 mass % tin oxide SnO.) The TFT substrate is connected to a driver circuit 13 and a control circuit 14 through a TAB tape 12.
The opposite substrate 2 is an insulating glass plate 1b, which has a common electrode 7 formed over the entire surface thereof facing the TFT substrate 1, color filters 8 opposite to the transparent pixel electrodes 5, and light shielding films 9 opposite to the TFTs 4 and the wiring 6 on the TFT substrate 1. The opposite substrate 2 additionally has an alignment layer 11 to orient in a desired direction the liquid crystal molecules (not shown) contained in the liquid crystal layer 3.
The TFT substrate 1 and the opposite substrate 2 have polarizers 10a and 10b, respectively, on their outer sides (opposite to the liquid crystal layer 3).
The liquid crystal panel 100 is designed such that the liquid crystal molecules in the liquid crystal layer 3 are properly oriented by the electric field generated between the opposite substrate 2 and the transparent pixel electrodes 5 and the oriented molecules modulate the light passing through the liquid crystal layer 3. In this way the amount of light passing through the opposite substrate 2 is controlled to produce images.
The following is a description of the structure and working principle of a conventional amorphous silicon TFT substrate used for liquid crystal panels, which is given with reference to FIG. 2. FIG. 2 is an enlarged view showing part A in FIG. 1.
There is shown in FIG. 2 the scanning line (gate thin film wiring) 25 formed on the glass plate (not shown). Part of the scanning line 25 functions as the gate electrode 26 that turns on and off the TFT. The gate electrode 26 is covered with the gate insulating film 27 of silicon nitride. There is also shown the signal line 34 (or the source-drain wiring) that intersects with the scanning line 25, with the gate insulating film 27 interposed between them. Part of the signal line 34 functions as the TFT source electrode 28. On the gate insulating film 27 are sequentially formed the amorphous silicon channel film 33 of active semiconductor, the signal line 34 (or the source-drain wiring), and the interlayer insulating film 30 of silicon nitride (as a protective film). The liquid crystal panel mentioned above is called that of bottom gate type.
The amorphous silicon channel film 33 is composed of a doped phase (or n-layer) containing P (phosphorus) and an intrinsic layer (or i-layer or undoped layer) not containing P. In the pixel region above the gate insulating film 27 is the transparent electrode 5 of ITO film (In2O3 containing SnO). The drain electrode 29 of the TFT is in direct contact with the transparent pixel electrode 5 for electrical connection.
The TFT 4 is turned on as the gate electrode 26 is supplied with gate voltage through the scanning line 25. The driving voltage, which has previously been supplied to the signal line 34, is supplied from the source electrode 28 to the transparent pixel electrode 5 through the drain electrode 29. As the transparent pixel electrode 5 is supplied with driving voltage at a certain level, an electric potential occurs between the transparent pixel electrode 5 and the opposite electrode 2 to orient the liquid crystal molecules in the liquid crystal layer 3 (for light modulation), as explained above with reference to FIG. 1.
The TFT substrate 1 conventionally has the source-drain wiring (electrically connected to the source-drain electrodes) and the scanning line 25 (electrically connected to the gate electrode 26) formed from thin film of Al-based alloy (such as Al—Nd) which is easy to work. The Al-based alloy, however, poses a problem with RC delay (slow transmission of electric signals through the wiring) as the liquid crystal display becomes larger than before. Thus, there is an increasing demand for replacement of Al-based alloy with a low-resistance material. Now, pure copper or Cu—Ni alloy is attracting attention which has a lower electrical resistance than Al-based alloy containing 2.0 at % of Nd.
The wiring of pure copper needs a barrier metal layer formed thereunder. In the case where the source-drain wiring 34, the gate electrode 26, and the scanning line 25 are formed from pure copper, it is necessary to form thereunder the respective barrier metal layers 51, 52, and 53 of high-melting metal, such as Mo, Cr, Ti, and W, as shown in FIG. 2. Patent Documents 1 to 6 disclose technologies to form the source-drain electrode with such a barrier metal layer. The disclosure is concerned typically with a dual-layer structure composed of a Mo layer (about 50 nm thick as a lower barrier metal layer) and a pure copper layer or a cooper alloy layer (about 150 nm thick) sequentially formed on top of the other.
The lower barrier metal layer 53 is interposed between the amorphous silicon channel layer 33 and the source-drain wiring 34 of pure copper or copper alloy as shown in FIG. 2. The main reason for this is to prevent mutual diffusion of Si and Cu at the interface between the pure copper thin film and the amorphous silicon channel thin film. (The interface may occasionally be referred simply to as interface.)
To be more precise, the pure copper thin film or copper alloy thin film and the amorphous silicon channel thin film, which are in direct contact with each other, will cause copper to diffuse into silicon and vice versa at the time of heat treatment, such as sintering and annealing, in the last stage of TFT forming. Such diffusion remarkably deteriorates the semiconductor performance, reduces the ON current, increases the OFF current (or leak current that flows while the TFT is turned off), or decreases the switching speed of the TFT. The result is poor TFT characteristics and poor display performance. The mutual diffusion of Cu and Si can be effectively avoided by the lower barrier metal layer 53.
The wiring formed from pure copper or copper alloy may separate from the amorphous silicon channel thin film 33, resulting in disconnection. This is due to poor adhesion between copper and amorphous silicon. Good adhesion is achieved by interposing a lower barrier metal layer 53 between pure copper or copper alloy and the amorphous silicon channel thin film 33.
However, forming the lower barrier metal layer 53 as mentioned above needs, in addition to the film-forming apparatus for the wiring of pure copper or copper alloy, a film-forming apparatus for the barrier metal layer. To be concrete, it is necessary to use a film-forming apparatus equipped with an additional chamber for the barrier metal layer. Such an apparatus may be a cluster tool having more than one film-forming chamber connected to a transfer chamber. The barrier metal layer adds up to production cost and lowers productivity to a nonnegligible extent as the cost of mass-produced liquid crystal displays decreases.
Thus, the lower barrier metal layer raises production cost and lowers productivity because it needs an extra film-forming chamber in addition to the film-forming sputtering apparatus for the gate electrode, source electrode, and drain electrode.
This situation has aroused interest in a new electrode material that eliminates the necessity of barrier metal layer and permits the source-drain electrodes to be connected directly to the semiconductor layer such as amorphous silicon channel thin film. Patent Documents 7 to 11 disclose technologies that do not need the barrier metal layer when pure aluminum or aluminum alloy is used for wiring, although they are not concerned with pure copper or copper alloy.
The foregoing problem is encountered in not only liquid crystal display devices but also amorphous silicon TFT substrates in common. It is also encountered in TFT substrates with semiconductor layers of polycrystalline silicon.
Patent Document 1:
Japanese Patent Laid-open No. Hei-7-66423
Patent Document 2:
Japanese Patent Laid-open No. 2001-196371
Patent Document 3:
Japanese Patent Laid-open No. 2002-353222
Patent Document 4:
Japanese Patent Laid-open No. 2004-133422
Patent Document 5:
Japanese Patent Laid-open No. 2004-212940
Patent Document 6:
Japanese Patent Laid-open No. 2005-166757
Patent Document 7:
Japanese Patent Laid-open No. Hei-11-337976
Patent Document 8:
Japanese Patent Laid-open No. Hei-11-283934
Patent Document 9:
Japanese Patent Laid-open No. Hei-11-284195
Patent Document 10:
Japanese Patent Laid-open No. 2004-214606
Patent Document 11:
Japanese Patent Laid-open No. 2003-273109